A dual-port SRAM has one input port for writing data information into the memory device and a second output port for reading data information out of the memory device. A dual-port configuration allows asynchronous reading and writing operations to be performed at the same time. The memory cells of an SRAM are arranged as columns and rows. For writing a data information bit into a particular memory cell a write bit line provides the information bit to an entire column of memory cells. A particular one of the memory cells in the column is selected for storing the information bit with a row selection signal provided on a write word line. For reading the contents of a particular memory cell, the particular memory cell in a column is selected for reading with a row selection signal provided on a read word line.
The overall performance of a dual-port RAM integrated-circuit device is often limited by the performance of the sense amplifiers and column selection circuits which are used to sense the charge stored in a particular memory cell. To obtain improvements in read times for a given memory cell design, the speed of the sense amplifiers must be improved. As higher speeds are demanded, RAM device architectures need to be redesigned to meet 140-200 MHz read access time requirements without changing the design of the actual memory cells. Designers of integrated-circuit memory devices continue to make memory cells and their associated multiplexing transistors smaller and smaller as the number of bits in the memory devices continue to increase. This means that the resistance of memory cells and their associated addressing circuits continue to increase so that switching time constants also tend to increase.
As higher operating speeds are required in SRAM memory designs, a problem arises. The problem is that the rates of charging and discharging the read bit lines of SRAM memory devices are limited. This is because the read bit lines are series connected from high-resistance memory cells through high-resistance Y MUX transistors to sense amps, which are typically passive receivers and which do not supply any charge to assist the bit line. Some synchronous, or clocked, sense amps do provide some assistance when HIGH bits in memory cells are being sensed. Problems with sensing LOW bits in the memory cells limit the frequency response of such memory devices.